`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:22:09 04/01/2014 
// Design Name: 
// Module Name:    CLK_div25MHz 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CLK_CPU(output reg CLK_out,
						  input CLK
    );
parameter high = 15;	 
reg [high:0] counter = 0;

always@(posedge CLK) begin
	counter <= counter +1'b1;
	CLK_out <= counter[high];
	
end

endmodule
